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wide range input, dual/two-phase, dc-to-dc synchronous buck controller ADP1850 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features wide range input: 2.75 v to 20 v power stage input voltage: 1 v to 20 v output voltage range: 0.6 v up to 90% v in output current to more than 25 a per channel accurate current sharing between channels (interleaved) programmable frequency: 200 khz to 1.5 mhz 180 phase shift between channels for reduced input capacitance 0.85% reference voltage accuracy from ?40c to +85c integrated boost diodes power saving mode (psm) at light loads accurate power good with internal pull-up resistor accurate voltage tracking capability independent channel precision enable overvoltage and overcurrent limit protection externally programmable soft start, slope compensation and current sense gain synchronization input thermal overload protection input undervoltage lockout (uvlo) available in 32-lead 5 mm 5 mm lfcsp applications high current single and dual output intermediate bus and point of load converters requiring sequencing and tracking capability, including converters for: point-of-load power supplies telecom base station and networking consumer industrial and instrumentation healthcare and medical general description the ADP1850 is a configurable dual output or two-phase, single output dc-to-dc synchronous buck controller capable of running from commonly used 3.3 v to 12 v (up to 20 v) voltage inputs. the device operates in current mode for improved transient response and uses valley current sensing for enhanced noise immunity. the architecture enables accurate current sharing between interleaved phases for high current outputs. the ADP1850 is ideal in system applications requiring multiple output voltages: the ADP1850 includes a synchronization fea- ture to eliminate beat frequencies between switching devices; provides accurate tracking capability between supplies and includes precision enable for simple, robust sequencing. the ADP1850 provides high speed, high peak current drive capability with dead-time optimization to enable energy efficient power conversion. for low load operation, the device can be configured to operate in power saving mode (psm) by skipping pulses and reducing switching losses to improve the energy efficiency at light load and standby conditions. the accurate current limit (6%) allows the power architect to design within a narrower range of tolerances and can reduce overall converter size and cost. the ADP1850 provides a configurable architecture capable of wide range input operation to provide the designer with maximum re-use opportunities and improved time to market. additional flexibility is provided by external programmability of loop compensation, soft start, frequency setting, power saving mode, current limit and current sense gain can all be programmed using external components. the ADP1850 includes a high level of integration in a small size package. the start-up linear regulator and the boot-strap diode for the high side drive are included. protection features include: undervoltage lock-out, overvoltage, overcurrent/short-circuit and over temperature. the ADP1850 is available in a compact 32-lead lfcsp 5 mm 5 mm thermally enhanced package. typical operation circuit ramp1 r ramp1 vin dh1 bst1 sw1 ilim1 fb1 dl1 pgnd1 ramp2 dh2 bst2 sw2 ilim2 fb2 dl2 pgnd2 en1 en2 vdl vcco trk1 trk2 sync freq comp1 comp2 ss1 ss2 agnd r csg1 r11 r12 r21 r22 m1 m2 r csg2 m3 l2 l1 v out1 v out2 v in v in m4 r ramp2 pgood1 pgood2 ADP1850 hi lo 09440-001 figure 1. single phase circuit
ADP1850 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical operation circuit ................................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 simplified block diagram ............................................................... 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 control architecture .................................................................. 12 oscillator frequency .................................................................. 12 modes of operation ................................................................... 13 synchronization .......................................................................... 13 synchronous rectifier and dead time ................................... 14 input undervoltage lockout ..................................................... 14 internal linear regulator .......................................................... 14 overvoltage pro tection .............................................................. 14 power good ................................................................................. 14 short circuit and current limit protection ........................... 15 sh utdown control ...................................................................... 15 thermal overload protection ................................................... 15 applications information .............................................................. 16 setting the output voltage ........................................................ 16 soft start ...................................................................................... 16 setting the current limit .......................................................... 16 accurate current limit sensing ............................................... 17 setting the slope compensation .............................................. 17 setting the current sense gain ................................................ 17 input capacitor selection .......................................................... 18 input filter ................................................................................... 18 boost capacitor selection ......................................................... 18 inductor selection ...................................................................... 18 output capacitor selection ....................................................... 19 mosfet selection ..................................................................... 19 loop compensation (single phase operation) ..................... 21 configuration and loop compensation (dual - phase operation) ................................................................................... 22 switching noise and overshoot reduction ............................ 22 voltage tracking ......................................................................... 23 indepdendent power stage input voltage ............................... 24 pcb layout guidelines .................................................................. 25 mosfets, input bulk capacitor, and bypass capacitor ...... 25 high current an d current sense paths ................................... 25 signal paths ................................................................................. 25 pgnd plane ................................................................................ 25 feedback and curre nt limit sense paths ............................... 25 switch node ................................................................................ 26 gate driver paths ....................................................................... 26 output capaci tors ...................................................................... 26 typical operating circuits ............................................................ 27 outline dimensions ....................................................................... 31 ordering guid e .......................................................................... 31 revision history 11 /10 rev ision 0: initial version
ADP1850 rev. 0 | page 3 of 32 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc ). v in = 12 v. the specifications a re valid for t j = ? 40 c to +1 25c, unless otherwise specified. typical values are at t a = 25c . table 1 . parameter symbol conditions min typ max unit power supply input voltage v in 2.75 20 v undervoltage lockout thresh old in uvlo v in rising 2.45 2.6 2.75 v v in falling 2.4 2.5 2.6 undervoltage lockout hysteresis 0.1 v quiescent current i in en1 = en2 = v in = 12 v, v fb = v cco in pwm mode (no switching) 4.5 5 .8 ma en1 = en2 = v in = 12 v, v fb = v cco in psm mode 2.8 ma shutdown current i in_sd en1 = en2 = gnd, v in = 5.5 v or 20 v 100 200 a error amplifier fb x input bias current i fb ?100 +1 +100 na transconductance g m sink or source 1 a 385 550 715 s trk1, trk2 input bias current i trk 0 v v trk1 /v trk2 5 v ?100 +1 +100 na current sense amplifier gain a cs gain resistor connected to dl x , r csg = 47 k? 5% 2.4 3 3.6 v/v gain r esistor connected to dl x , r csg = 22 k? 5% 5.2 6 6.9 v/v default setting, r csg = open 10.5 12 13.5 v/v gain resistor connected to dl x , r csg = 100 k? 5% 20.5 24 26.5 v/v output characterictistics feedback accuracy voltage v fb t j = ? 40c t o +85 c, v fb = 0.6 v ?0.85% + 0.6 +0.85% v t j = ?40 c to +125 c, v fb = 0.6 v ?1.5% + 0.6 +1.5% v line regulation of pwm v fb / v in 0.015 %/v load regulation of pwm v fb / v comp v comp range = 0.9 v to 2.2 v 0.3 % oscillator frequency f sw r fr eq = 340 k ? to agnd 170 200 235 khz r freq = 78.7 k ? to agnd 720 800 880 khz r freq = 39.2 k ? to agnd 1275 1500 1725 khz freq to agnd 235 300 345 khz freq to vcco 475 600 690 khz sync input frequency range f sync f sync = 2 f sw 400 3000 khz sync input pulse width t syncmin 100 ns sync pin capacitance to gnd c sync 5 pf linear regulator vcco output voltage i vcco = 100 ma 4.7 5.0 5.3 v vcco load regulation i vcco = 0 ma to 100 ma, 35 mv vcco line regulation v in = 5.5 v to 20 v, i vcco = 20 ma 10 mv vcco current limit 1 vcco drops to 4 v from 5 v 350 ma vcco short - circuit current 1 vcco < 0.5 v 370 400 ma vin to vcco dropout voltage 2 v dropout i vcco = 100 ma, v in 5 v 0.33 v logic inputs en1, en2 en1/en2 rising 0.57 0.63 0.68 v en1, en2 hysteresis 0.03 v en1, en2 input leakage current i en v in = 2.75 v to 20 v 1 200 na sync logic input low 1.3 v sync logic input high 1.9 v sync input p u ll - down resistance r sync 1 m?
ADP1850 rev. 0 | page 4 of 32 parameter symbol conditions min typ max unit gate drivers dhx rise time c dh = 3 nf, v bst ? v sw = 5 v 16 ns dhx fall time c dh = 3 nf, v bst ? v sw = 5 v 14 ns dlx rise time c dl = 3 nf 16 ns dlx fall time c dl = 3 nf 14 ns dhx to dlx dead time external 3 nf is connected to dhx and dlx 25 ns dhx or dlx driver r on , sourcing current 1 r on_source sourcing 2 a with a 100 ns pulse 2 sourcing 1 a with a 100 ns pulse, v in = 3 v 2.3 dhx or dlx driver r on , tempco tc ron v in = 3 v or 12 v 0.3 %/ o c dhx or dlx driver r on , sinking current 1 r on_sink sinking 2 a with a 100 ns pulse 1.5 sinking 1 a with a 100 ns pulse, v in = 3 v 2 dhx maximum duty cycle f sw = 300 khz 90 % dhx maximum duty cycle f sw = 1500 khz 50 % minimum dhx on time f sw = 200 khz to 1500 khz 135 ns minimum dhx off time f sw = 200 khz to 1500 khz 335 ns minimum dlx on time f sw = 200 khz to 1500 khz 285 ns compx voltage range compx pulse skip threshold v comp,thres in pulse skip mode 0.9 v compx clamp high voltage v comp,high 2.25 v thermal shutdown thermal shutdown threshold t tmsd 155 ?c thermal shutdown hysteresis 20 ?c overvoltage and power good thresholds fbx overvoltage threshold v ov v fb rising 0.635 0.65 0.665 v fbx overvoltage hysteresis 30 mv fbx undervoltage threshold v uv v fb falling 0.525 0.55 0.578 v fbx undervoltage hysteresis 30 mv trkx input voltage range 0 5 v fbx to trkx offset voltage trkx = 0.1 v to 0.57 v, offset = v fb ? v trk ?10 0 +10 mv soft start ssx output current i ss during start-up 4.6 6.5 8.4 a ssx pull-down resistor during a fault condition 3 k fbx to ssx offset v ss = 0.1 v to 0.6 v, offset = v fb ? v ss ?10 +10 mv pgoodx pgoodx pull-up resistor r pgood internal pull-up resistor to vcco 12.5 k pgoodx delay 12 s over voltage or under voltage this is the minimum duration required to trip the pgood signal 10 s minimum duration ilim1, ilim2 threshold voltage 1 relative to pgndx ?5 0 +5 mv ilim1, ilim2 output current ilimx = pgndx 47 50 53 a current sense blanking period after dlx goes high, current limit is not sensed during this period 100 ns integrated rectifier (boost diode) resistance at 20 ma forward current 16 zero current cross offset (swx to pgndx) 1 in pulse skip mode only, f sw = 600 khz 0 2 4 mv 1 guaranteed by design. 2 connect v in to vcco when 2.75 v < v in < 5.5 v.
ADP1850 rev. 0 | page 5 of 32 absolute maximum ratings table 2. parameter rating vin, en1/en2, ramp1/ramp2 21 v fb1/fb2, comp1/comp2, ss1/ss2, trk1/trk2, freq, sync, vcco, vdl, pgood1/pgood2 ?0.3 v to +6 v ilim1/ilim2, sw1/sw2 to pgnd1/pgnd2 ?0.3 v to +21 v bst1/bst2, dh1/dh2 to pgnd1/pgnd2 ?0.3 v to +28 v dl1/dl2 to pgnd1/pgnd2 ?0.3v to vcco + 0.3 v bst1/bst2 to sw1/sw2 ?0.3 v to +6 v bst1/bst2 to pgnd1/pgnd2 20 ns transients 32 v sw1/sw2 to pgnd1/pgnd2 20 ns transients 25 v dl1/dl2, sw1/sw2, ilim1/ilim2 to pgnd1/pgnd2 20 ns negative transients ?8 v pgnd1/pgnd2 to agnd ?0.3 v to +0.3 v pgnd1/pgnd2 to agnd 20 ns transients ?8 v to +4 v ja on multilayer pcb (natural convection) 1, 2 32.6c/w operating junction temperature range 3 ?40c to +125c storage temperature range ?65c to +150c maximum soldering lead temperature 260c 1 measured with exposed pad attached to pcb. 2 junction-to-ambient thermal resistance ( ja ) of the package was calculated or simulated on multilayer pcb. 3 the junction temperature, t j , of the device is dependent on the ambient temperature, t a , the power dissipation of the device, p d , and the junction-to- ambient thermal resistance of the package, ja . maximum junction temperature is calculated from the ambient temper ature and power dissipation using the formula: t j = t a + p d ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to gnd. esd caution
ADP1850 rev. 0 | page 6 of 32 simplified block diagram duplicate for channel 2 bst1 pgnd1 + ? + ? + ? + ? + ? + ? fb1 0.6v ov uv pgood1 current sense amplifier dh1 dl1 ilim1 sw1 v ref = 0.6v 6.5 a + + ? error amplifier fb1 comp1 ss1 pwm comparator slope comp and ramp generator current limit control vdl ramp1 50a 5v g m ov1 + trk1 cs gain driver logic control and state machine over_lim1 pulse skip over_lim1 ldo logic en1 en2 vin uvlo oscillator freq sync ph1 ph2 ref vcco ov uv 0.6v thermal shutdown agnd 0.6v + ? + ? vcco vdl fault ov1 logic over_lim1 ov1 en1 en1_sw logic uv1 1k? 0.9v dcm zero cross detect 12k? a v = 3, 6, 12, 24 vcco sync en1_sw en2_sw 1m ? ? + 09440-003 figure 2.
ADP1850 rev. 0 | page 7 of 32 pin configuration and function descripti ons 09440-004 24 sw1 23 dh1 22 pgnd1 21 dl1 20 dl2 19 pgnd2 18 dh2 17 sw2 1 2 3 4 5 6 7 8 en1 sync vin vcco vdl agnd freq en2 9 10 11 12 13 14 15 16 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 32 31 30 29 28 27 26 25 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 ADP1850 top view (not to scale) notes 1. connect the bottom exposed pad of the lfcsp package to system agnd plane. figure 3. pin configuration table 3 . pin function descrip tions pin o. mneonic description 1 en1 enable input for channel 1. drive en1 high to turn on the channel 1 controller, and drive en1 low to turn off the channel 1 controller . tie en1 to vin for automatic startup. for a precision uvlo, put an appropriate ly sized re sistor divider from vin to agnd and tie the midpoint to this pin. 2 sync frequency synchronization input. accepts an external signal between 1 and 2.3 of the internal oscillator frequency, f sw , set by the freq pin. the controller operates in forced pwm when a signal is detected at sync or when sync is high. the resulting switching frequency is ? of the sync frequency. when sync is low or left floating, the controller operates in pulse skip mode. for dual - phase operation, connect sync to a logi c high or an external clock. 3 vin connect to main power supply . bypass with a 1 f or larger ceramic capacitor connected as close to this pin as possible and pgnd x. 4 vcco output of the internal low dropout regulator (ldo). bypass vcco to agnd with a 1 f or larger ceramic capacitor. the vcco output remains active even when en1 and en2 are low. for operation with vin below 5 v, vin may be shorted to vcco. do not use the ldo to power other auxiliary system loads. 5 vdl power supply for the low - side drive r. bypass vdl to pgnd x with a 1 f or greater ceramic capacitor. connect vcco to vdl. 6 agnd analog ground. 7 freq sets the desired operating frequency between 200 khz and 1.5 mhz with one resistor between freq and agnd. connect freq to agnd for a prepr ogrammed 300 khz or freq to vcco for 600 khz operating frequency. 8 en2 enable input for channel 2. drive en2 high to turn on the channel 2 controller, and drive en2 low to turn off the channel 2 controller . tie en2 to vin for automatic startup. for a pre cision uvlo, put an appropriately sized resistor divider from vin to agnd, and tie the midpoint to this pin. 9 trk2 tracking input for channel 2. connect trk2 to vcco if tracking is not used. 10 fb2 output voltage feedback for channel 2. connect to outp ut 2 via a resistor divider. 11 comp2 compensation node for channel 2. output of channel 2 error amplifier. connect a series resistor - capacitor network from comp2 to agnd to compensate the regulation control loop. 12 ramp2 connect a resistor from ramp2 to vin to set up a ramp current for slope compensation in channel 2 . the voltage at ramp2 is 0.2 v. this pin is high impedance when the channel is disabled. 13 ss2 soft start input for channel 2. connect a capacitor from ss2 to agnd to set the soft start period. the nod e is internally pulled up to 5 v with a 6.5 a current source. 14 pgood2 power good. open - drain power - good indicator logic output with an internal 12 k ? resistor connected between pgood2 and vcco. pgood2 is pulled to ground when the channel 2 output is outside the regulation window. an external pull - up resistor is not required.
ADP1850 rev. 0 | page 8 of 32 pin no. mnemonic description 15 ilim2 current limit sense comparator inverting input for channel 2. connect a resistor between ilim2 and sw2 to set the current limit offset. for accurate current limit sensing, connect ilim2 to a current sense resistor at the source of the low - side mosfet. 16 bst2 b oot - strapped upper rail of high side internal driver for channel 2. connect a multilayer ceramic capacitor ( 0.1 f to 0.22 f ) between bst2 and sw2. there is an internal boost rectifier connected between vdl and bst2. 17 sw2 switch node for channel 2. connect to source of the high - side n - channel mo sfet and the drain of the low - side n- channel mosfet of channel 2. 18 dh2 high - side switch gate driver output for channel 2. capable of driving mosfets with total input capacitance up to 20 nf. 19 pgnd2 power ground for channel 2. ground for internal channel 2 driver. differential current is sensed between sw2 and pgnd2. use the kelvin sensing connection technique between pgnd2 and source of the low - side mosfet. 20 dl2 low - side synchronous rectifier gate driver output for channel 2. to set the gain of the current sense amplifier, connect a resistor between dl2 and pgnd2. capable of driving mosfets with a total input capacitance up to 20 nf. 21 dl1 low - side synchronous rectifier gate driver output for channel 1. to set the gain of the current sense amplif ier, connect a resistor between dl1 and pgnd1 . capable of driving mosfets with a total input capacitance up to 20 nf. 22 pgnd1 power ground for channel 1. ground for internal channel 1 driver. differential current is sensed between sw1 and pgnd1. use the kelvin sensing connection technique between pgnd1 and source of the low - side mosfet. 23 dh1 high - side switch gate driver output for channel 1. capable of driving mosfets with a total input capacitance up to 20 nf. 24 sw1 power switch node for channel 1. connect to source of the high - side n - channel mosfet and the drain of the low - side n - channel mosfet of channel 1. 25 bst1 boot - strapped upper rail of high side internal driver for channel 1. connect a multilayer ceramic capacitor (0.1 f to 0.22 f ) betwe en bst1 and sw1. there is an internal boost diode or rectifier connected between vdl and bst1. 26 ilim1 current limit sense comparator inverting input for channel 1. connect a resistor between ilim1 and sw1 to set the current limit offset. for accurate current limit sensing, connect ilim1 to a current sense resistor at the source of the low - side mosfet. 27 pgood1 power good. open - drain power - good indicator logic output with an internal 12 k ? resistor connected between pgood1 and vcco. pgood1 is pulled to ground when the channel 1 output is outside the regulation window. an external pull - up resistor is not required. 28 ss1 soft start input fo r channel 1. connect a capacitor from ss1 to agnd to set the soft start period. this nod e is internally pulled up to 5 v with a 6.5 a current source. 29 ramp1 connect a resistor from ramp1 to vin to set up a ramp current for slope compensation in channe l 1 . the voltage at ramp2 is 0.2 v. this pin is high impedance when the channel is disabled. 30 comp1 compensation node for channel 1. output of channel 1 error amplifier. connect a series resistor - capacitor network from comp1 to agnd to compensate the r egulation control loop. 31 fb1 output voltage feedback for channel 1. connect to output 1 via a resistor divider. 32 trk1 tracking input for channel 1. connect trk 1 to vcco if tracking is not used. 33 (epad) exposed pad (epad) connect the bottom expos ed pad of the lfcsp package to the system agnd plane.
ADP1850 rev. 0 | page 9 of 32 typical performance characteristics 100 0 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 efficiency (%) load (a) v o = 3.3v, psm v o = 1.8v, psm v o = 3.3v, pwm v o = 1.8v, pwm v in = 12v, 600khz 09440-005 figure 4 . efficiency plot of figure 44 100 0 10 20 30 40 50 60 70 80 90 0.01 0. 1 1 10 efficiency (%) load (a) v o = 5v, psm v o = 1.8v, psm v o = 5v, pwm v o = 1.8v, pwm v in = 12v, 750khz 09440-006 figure 5 . efficiency plot of figure 45 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 2.5 3.0 3. 5 4.0 4.5 5. 0 vcco (v) v in (v) 50ma load 100ma load 09440-007 figure 6 . ldo load regulation 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5 7 9 11 13 15 17 vcco (v) v in (v) no load on ldo 100ma load on ldo 09440-008 figure 7 . ldo line regulation 0 1 2 3 4 5 6 0 1 2 3 4 5 6 vcco (v) v in (v) 09440-009 figure 8 . vcco vs. v in ch1 10v ch3 5v ch2 10v m1s a ch1 5.60v sw1 sw2 sync 600khz 1 3 2 09440-010 figure 9 . an example of synchr onization, f sync = 600 khz
ADP1850 rev. 0 | page 10 of 32 ch1 20mv b w ch4 5a ? m200s a ch4 11.5a 1 4 v in = 12v v out = 3.3v 8a to 13a step load output response 09440-011 figure 10. step load transient of figure 44 2 ch3 1v ch2 5v ch1 5v ch4 1a ? m1ms a ch1 2.4v v in = 12v v out = 1.8v output precharged to 1v dh1 dl1 vout1 il1 1 3 4 09440-012 figure 11. soft start into precharged output ch3 1v ch2 2v ch1 10v ch4 1v m10ms a ch2 1.52v c ss = 100nf v out (ch3) ss (ch4) en sw 1 2 3 4 09440-013 figure 12. enable start-up function ch3 2v ch2 2v ch1 10v ch4 2v ? m10ms a ch2 3.76v sw1 pgood1 vcco (ch3) v out , preloaded (ch4) 1 2 3 4 09440-014 figure 13. thermal shutdown waveform ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 3 5 7 9 11 13 15 17 19 21 change in f sw (%) v in (v) referenced at v in = 2.75v 600khz 300khz 850khz 09440-015 figure 14. change in f sw vs. v in ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?40 ?15 10 35 60 85 110 135 change in f sw (%) temperature (c) v in = 12v; referenced at 25c 09440-016 figure 15. f sw vs. temperature
ADP1850 rev. 0 | page 11 of 32 50 100 150 200 250 300 350 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 time (ns) v in (v) dh minimum off time dh minimum on time 09440-017 figure 16 . t ypical dh minimum on time and off time ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 ?15 10 35 60 85 110 135 change in minimum on/off time (%) temperature ( c) dh minimum on time dh minimum off time 09440-018 figure 17 . dh minimum on time and off time over t emperature 25 35 34 33 32 31 30 29 28 27 26 ?40 ?20 0 20 40 60 80 100 120 140 dead time (ns) temperature (c) v in = 12v output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between sw falling edge and dl rising edge, including diode recovery time 09440-019 figure 18 . dead time vs. temperature 25 45 43 41 39 37 35 33 31 29 27 0 20 15 10 5 dead time (ns) v in (v) t a = 25c output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between sw falling edge and dl rising edge, including diode recovery time 09440-020 figure 19 . dead time vs. v in 400 420 440 460 480 500 520 540 560 580 600 ?40 ?15 10 35 60 85 110 135 g m (s) temperature ( c) v in = 2.75v to 20v 09440-021 figure 20 . g m of error amplifier vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?40 ?15 10 35 60 85 110 135 driver resistance ( ?) temperature ( c) v in = 2.75v, sourcing v in = 12v, sourcing v in = 2.75v, sinking v in = 12v, sinking 09440-022 figure 21 . driver resistance vs. temperature
ADP1850 rev. 0 | page 12 of 32 theory of operation the adp 1850 is a current m ode , dual - channel, step - down switching controller with i ntegrated mosfet drivers for exte r nal n- channel synchronous power mosfets. the two outputs are phase shifted 180 . this reduces the input rms ripple current, thus minimizing required input capacitance. in addition, the two outputs can be combined for dual - phase pwm operation that can deliver more than 50 a output current and the two channels are optimized for current sharing. the adp 1850 can be set to operate in pulse skip high efficiency mode (power saving mode) under light load or in forced pwm. the inte grated boost diodes in the adp 1850 reduce the overall system cost and component count. the adp 1850 includes program mable soft start, output overvoltage protection, program - mable current limit, power good, and tracking function. the adp 1850 can be set to op erate in any switching frequency between 200 khz and 1.5 mhz with one external resistor. control architecture the adp 1850 is based on a fixed frequency , current mode , pwm control architecture. the inductor current is sensed by the voltage drop measured a cross the external low - side mosfet , r dson , during the off period of the switching cycle (valley inductor current). the current sense signal is further processed by the current sense amplifier. the output of the current sense amplifier is held, and the emul ated current ramp is multiplexed and fed into the pwm comparator as shown in figure 22 . the valley current information is captured at the end of the off period, and the emulated current ramp is applied at that po int when the next on cycle begins. an error amplifier integrates the error between the feedback voltage and the generated error voltage from the comp x pin (from error amp lifier in figure 22 ). ff osc q q s r a cs v cs v in v in a r r ramp i ramp c r from error amp to drivers from low-side mosfet 09440-023 figure 22 . simplified control architecture as shown in figure 22 , the emulated current ramp is generated inside the ic but offers programmability through the rampx pin . selecting an appropriate value resi stor from v in to the ramp x pin programs a desired slope compensation value and, at the same time, provides a feed forward feature. the benefits realized by deploying this type of control scheme are that there is no need to worry about the turn - on current s pike corrupting the current ramp. also, the current signal is stable because the current signal is sampled at the end of the turn - off period, which gives time for the switch node ringing to settle. other benefits of using current mode control scheme still apply, such as simplicity of loop compensation. control logic enforces antishoot - through operation to limit cross conduction of the internal drivers and external mosfets. oscillator frequency the internal oscillator frequency, which ranges from 200 khz to 1.5 mhz, is set by an external resistor, r freq , at the freq pin. some popular f sw values are shown in table 4 , and a graph - ical relationship is shown in figure 23 . fo r instance, a 78.7 k ? resistor sets the oscillator frequency to 800 khz. furthermore, connecting freq to agnd or freq to vcco sets the oscil - lator frequency to 300 khz or 600 khz, respectively. for other frequencies that are not listed in table 4 , the values of r freq and f sw can be obtained from figure 23 , or use the following empirical formula to calculate these values: 065 .1 ) khz ( 96568)k( ? = sw feq f r table 4 . setting the oscillator frequency r freq f sw (typical) 332 k ? 200 khz 78.7 k ? 800 khz 60.4 k ? 1000 khz 51 k ? 1200 khz 40.2 k ? 1500 khz freq to agnd 300 khz freq to vcco 600 khz 10 60 110 160 210 260 310 360 410 100 400 700 1000 1300 1600 1900 r freq (k ?) f sw (khz) r freq (k ? ) = 96,568 f sw (khz) ?1.065 09440-024 figure 23 . r freq vs. f sw
ADP1850 rev. 0 | page 13 of 32 modes of operation the sync pin is a multifunctional pin. pwm mode is en abled when sync is connected to vcco or a high logic. with sync connected to ground or left floating, the pulse skip mode is enabled. switching sync from low to high or high to low on the fly causes the controller to transition from forced pwm to pulse sk ip mode or pulse skip mode to forced pwm, respec - tively, in two clock cycles. table 5 . mode of operation truth table sync pin mode of operation low pulse skip mode high forced pwm or two - phase operation no connect pulse skip mod e clock signal forced pwm or two - phase operation the adp 1850 has a pulse skip sensing circuitry that allows the controller to skip pwm pulses, thus , reducing the switching frequency at light loads and, therefore, maintaining high efficiency during a light load operation. the switching frequency is a fraction of the natural oscillator frequency and is automatically adjusted to regulate the output voltage. the resulting output ripple is larger than that of the fixed frequency forced pwm. figure 24 shows that the adp 1850 operates in psm under a very light load. pulse skip frequency under light load is dependent on the inductor , output capacitance, output load, and input and output voltages. ch3 20mv ch2 200mv ch1 10v ch4 2a ? m200 s a ch1 7. 8v sw1 comp1 (ch2) vout ripple inductor current 1 3 2 4 09440-025 figure 24 . example of pulse skip mode under light loa d when the output load is greater than the pu lse skip threshold current, that is, v comp reaches the threshold of 0.9 v , the adp 1850 exits the pulse skip mode of operation and enters the fixed frequen cy discontinuous conduction mode (dcm), as shown in figure 25 . when the load increases further, the adp 1850 enters ccm. ch3 20mv ch2 5v ch1 10v ch4 2a ? m1s a ch1 13.4v dh1 dl1 output ripple inductor current 1 2 3 4 09440-026 figure 25 . example of discontinuous conduction mode (dcm) wavef orm in forced pwm, the adp 1850 always operates in ccm at any load. the inducto r current is always continuous, thus , efficiency is poor at light loads. synchronization the switching frequency of the adp 1850 can be synchronized to an external clock by conne cting sync to a clock signal. the external clock should be between 1 and 2.3 of the internal oscillator frequency, f sw . the resulting switching frequency is ? of the external sync frequency because the sync input is divided by 2, and the resulting phases are used to clock the two channels alternately. in synchronization, the adp 1850 operates in pwm . when an external clock is detected at the first sync edge, the internal oscillator is reset, and the clock control shifts to sync. the sync edges then trigger subsequent clocking of the pwm outputs. the dh1/dh2 rising edges appear approximately 100 ns after the corresponding sync edge, and the frequency is locked to the external signal. depending on the start - up conditions of channel 1 and channel 2, either cha nnel 1 or channel 2 can be the first channel synchronized to the rising edge of the sync clock. if the external sync signal disappears during operation, the adp 1850 reverts to its internal oscillator. when the sync functi on is used, it is recommended to co nnect a pull - up resist or from sync to vcco so that when the sync signal is lost, the adp 1850 continues to operate in pwm.
ADP1850 rev. 0 | page 14 of 32 synchronous rectifier and dead time the synchronous rectifier (low-side mosfet) improves efficiency by replacing the schottky diode that is normally used in an asynchronous buck regulator. in the ADP1850, the antishoot- through circuit monitors the sw and dl nodes and adjusts the low-side and high-side drivers to ensure break-before-make switching which prevents cross-conduction or shoot-through between the high-side and low-side mosfets. this break- before-make switching is known as dead time, which is not fixed and depends on how fast the mosfets are turned on and off. in a typical application circuit that uses medium sized mosfets with input capacitance of approximately 3 nf, the typical dead time is approximately 30 ns. when small and fast mosfets with fast diode recovery time are used, the dead time can be as low as 13 ns. input undervoltage lockout when the bias input voltage, v in , is less than the undervoltage lockout (uvlo) threshold, the switch drivers stay inactive. when v in exceeds the uvlo threshold, the switchers start switching. internal linear regulator the internal linear regulator is low dropout (ldo) meaning it can regulate its output voltage, vcco. vcco powers up the internal control circuitry and provides power for the gate drivers. it is guaranteed to have more than 200 ma of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold mosfets driven at up to 1.5 mhz. vcco is always active and cannot be shut down by the en1 and en2 pins. bypass vcco to agnd with a 1 f or greater capacitor. because the ldo supplies the gate drive current, the output of vcco is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. the ldo has been optimized to handle these transients without overload faults. due to the gate drive loading, using the vcco output for other external auxiliary system loads is not recommended. the ldo includes a current limit well above the expected maximum gate drive load. this current limit also includes a short-circuit fold back to further limit the vcco current in the event of a short-circuit fault. the vdl pin provides power to the low-side driver. connect vdl to vcco. bypass vdl to pgndx with a 1 f (minimum) ceramic capacitor, which must be placed close to the vdl pin. for an input voltage less than 5.5 v, it is recommended to bypass the ldo by connecting vin to vcco, as shown in figure 26, thus eliminating the dropout voltage. however, if the input range is 4 v to 7 v, the ldo cannot be bypassed by shorting vin to vcco because the 7 v input has exceeded the maximum voltage rating of the vcco pin. in this case, use the ldo to drive the internal drivers, but keep in mind that there is a dropout when v in is less than 5 v. v in = 2.75v to 5.5v ADP1850 vin vcco 09440-027 figure 26. configuration for v in < 5.5 v overvoltage protection the ADP1850 has a built-in circuit for detecting output over- voltage at the fb node. when the fb voltage, v fb , rises above the overvoltage threshold, the low-side n-channel mosfet (nmosfet) is immediately turned on, and the high-side nmosfet is turned off until the v fb drops below the undervoltage threshold. this action is known as the crow- bar overvoltage protection. if the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the output is regulated to within typically +8% and ?8% of the regulation voltage. during an overvoltage event, the ss node discharges toward zero through an internal 3 k pull-down resistor. when the voltage at fbx drops below the undervoltage threshold, the soft start sequence restarts. figure 27 shows the overvoltage protection scheme in action in psm. ch1 20.0v ch2 5.00v ch3 1.00v ch4 10.0v m100s a ch1 10.0v 1 2 4 3 dh1 pgood1 vo1 = 1.8v shorted to 2v source vin 09440-028 figure 27. overvoltage protection in psm power good the pgoodx pin is an open-drain nmosfet with an internal 12 k pull-up resistor connected between pgoodx and vcco. pgoodx is internally pulled up to vcco during normal operation and is active low when tripped. when the feedback voltage, v fb , rises above the overvoltage threshold or drops below the undervoltage threshold, the pgoodx output is pulled to ground after a delay of 12 s. the overvoltage or undervoltage condition must exist for more than 10 s for pgoodx to become active. the pgoodx output also becomes active if a thermal overload condition is detected.
ADP1850 rev. 0 | page 15 of 32 short circuit and current limit protection when the output is shorted or the output cu rrent exceeds the current limit set by the current limit setting resistor ( between ilimx and swx) for eight consecutive cycles, the adp 1850 shuts off both the high - side a nd low - side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. the ss node discharges to zero through an internal 1 k ? resistor during an overcurrent or short - circuit event. figur e 28 shows that the adp 1850 on a high current application circuit is entering current limit hiccup mode when the output is shorted. ch3 500mv ch1 10v ch4 10a ? m2ms a ch1 11.2v sw1 ss1 inductor current 1 3 4 09440-029 figure 28 . current limit hiccup mode, 20 a current limit shutdown control the en1 and en2 pins are used to enable or disable channel 1 and channel 2 of the adp 1850 . the precision enable (minimum) thresho ld for en1/en2 is 0.57 v. when the voltage at en1/en2 rises above the threshold voltage, the adp 1850 is enabled and starts normal operation after the soft start period. and w hen the voltage at en1/en2 drops typically 30 mv (hysteresis) below the threshold voltage, the switchers and the internal circuits in the adp 1850 are turned off. note that en1/en2 cannot shut down the ldo at vcco, which is always active. for the purpose of start - up power sequencing, the startup of the adp 1850 can be programmed by connecting an appropriate resistor divider from the master power supply to the en1/en2 pin, as shown in figure 29 . for instance, if the desired start - up voltage from the master power supply is 10 v, r1 and r2 can be set to 156 k ? and 10 k?, respectively. ADP1850 fb1 or fb2 en1 or en2 r top r bot v out1 r1 r2 master supply voltage 09440-030 figure 29 . optional power - up sequencing circuit thermal overload pro tection the adp 1 850 has an internal temperature sensor that senses the junction temperature of the chip. when the junction temperature of the adp 1850 reaches approximately 155c, the adp 1850 goes into thermal shutdown, the converter is turned off, and ss discharges toward zero through an internal 1 k ? resistor. at the same time, vcco discharges to zero. when the junction temperature drops below 135c, the adp 1850 resumes normal operation after the soft start sequence.
ADP1850 rev. 0 | page 16 of 32 applications information setting the output voltage the output voltage is set using a resistive voltage divider from the output to fb. the voltage divider divides down the output voltage to the 0.6 v fb regulation voltage to set the regulation output voltage. the output voltage can be set to as low as 0.6 v and as high as 90% of the power input voltage. the maximum input bias current into fb is 100 na. for a 0.15% degradation in regulation voltage and with 100 na bias current, the low-side resistor, r bot , must be less than 9 k, which results in 67 a of divider current. for r bot , use a 1 k to 20 k resistor. a larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the fbx pin, while lower values cause increased quiescent current consumption. choose r top to set the output voltage by using the following equation: ? ? ? ? ? ? ? ? ? ? fb fb out bot top v vv rr where: r top is the high-side voltage divider resistance. r bot is the low-side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. the minimum output voltage is dependent on f sw and minimum dh on time. the maximum output voltage is dependent on f sw , the minimum dh off time, and the ir drop across the high-side nmosfet and the dcr of the inductor. for example, with f sw of 600 khz (or 1.67 s) and a minimum on time of 130 ns, the minimum duty cycle is approximately 7.8% (130 ns/1.67 s). if v in is 12 v and the duty cycle is 7.8%, then the lowest output is 0.94 v. as an example for the maximum output voltage, if v in is 5 v, f sw is 600 khz, and the minimum dh off time is 395 ns (335 ns dh off time plus approximately 60 ns total dead time), then the maximum duty cycle is 76%. therefore, the maximum output is approximately 3.8 v. if the ir drop across the high- side nmosfet and the dcr of the inductor is 0.5 v, then the absolute maximum output is 4.5 v (5 v ? 0.5 v), independent of f sw and duty cycle. soft start the soft start period is set by an external capacitor between ss1/ss2 and agnd. the soft start function limits the input inrush current and prevents output overshoot. when en1/en2 is enabled, a current source of 6.5 a starts charging the capacitor, and the regulation voltage is reached when the v oltage at ss1/ss2 reaches 0.6 v. the soft start period is approximated by ss ss c t a5.6 v6.0 ? the ssx pin reaches a final voltage equal to vcco. if the output voltage is precharged prior to turn-on, the ADP1850 prevents reverse inductor current, which discharges the output capacitor. once the voltage at ssx exceeds the regulation voltage (typically 0.6 v), the reverse current is reenabled to allow the output voltage regulation to be independent of load current. furthermore, in dual-phase operation, where ss1 is shorted to ss2, the current source is doubled to 13 a during the soft start sequence. when a controller is disabled, for instance, en1/en2 is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 3 k pull-down resistor. setting the current limit the current limit comparator measures the voltage across the low-side mosfet to determine the load current. the current limit is set by an external current limit resistor, r ilim , between ilimx and swx. the current sense pin, ilimx, sources nominally 50 a to this external resistor. this creates an offset voltage of r ilim multiplied by 50 a. when the drop across the low-side mosfet, r dson , is equal to or greater than this offset voltage, the ADP1850 flags a current limit event. because the ilimx current and the mosfet, r dson , vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. to do this, use the peak current in the inductor, which is the desired output current limit level plus ? of the ripple current, the maximum r dson of the mosfet at its highest expected temperature, and the minimum ilim current. keep in mind that the temperature coefficient of the mosfet, r dson , is typically 0.4%/ o c. a47 _ ? ? ? max dson lpk ilim ri r where: i lpk is the peak inductor current.
ADP1850 rev. 0 | page 17 of 32 accurate current lim it sensing r dson of the mosfet can vary by more than 50% over the temperature range. accu rate current limit sensing is achieved by add ing a current sense resistor from the source of the low - side mosfet to pgnd x . make sure that the power rating of the current sense resistor is adequate for the application . apply the previous equation and calculate r ilim by replacing r dson_max with r sense . figure 30 illustrates the implementation of accurate current limit sensing. v in ADP1850 dhx swx ilimx dlx r ilim r sense 09440-031 figure 30 . accurate current limit sensing setting the slope co mpensation in a current - mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. the external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the rampx pin. to implemen t the slope compensation, connect a resistor between rampx and the input voltage. the resistor, r ramp , is calculated by max dson cs ramp ra l r _ 9 107 = where: 7 10 9 is an internal parameter. l is the inductance (with units in h) of the inductor. r dson_max is t he low - side mosfet maximum on resistance. a cs is the gain, either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, of the current sense amplifier (see the setting the current sense gain section for more details). r dson is temperature dependent and can vary as much as 0.4%/ o c. choose r dson at the maximum operating temperature. the voltage at rampx is fixed at 0.2 v, and the current going in to rampx should be between 10 a and 160 a. make sure that the following condition is satis fied: a160 v2.0 a10 ? ? ? ramp in r v for instance, with an input voltage of 12 v, r ramp should not exceed 1.1 m ?. if the calculated r ramp produces less than 10 a , then select a n r ramp value that produces between 10 a and 15 a . figure 31 illustrates the connection of the slope compensation resistor, r ramp , and the curre nt sense gain resistor , r csg . v in ADP1850 dhx swx ilimx dlx r ilim r csg ramp r ramp 09440-032 figure 31 . slope compensation and cs gain connection setting the current sense gain the voltage drop across the external low - side mosfet is sensed by a current sense amplifier by multiplying the peak inductor current and the r dson of the mosfet. the result is then amplified by a gain factor of either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, which is programmable by an external resistor, r csg , connected to the dl x pin. this gain is sensed only during power - up and not during normal operation. the amplified voltage is summed with the slope compensation ramp voltage and fed into the pwm controller for a stable regulation voltage. the voltage range of the internal node, v cs , is between 0.4 v and 2.2 v. select the current sense gain such that the internal minimum amplified voltage (v csmin ) is above 0.4 v and the maximum amplified voltage (v csmax ) is 2.1 v. note that v csmin or v csmax is not the same as v comp , which has a range of 0.85 v to 2.25 v. make sure that the maximum v comp (v compmax ) does not exceed 2.2 v to account for temperature and part - to - part variations . see the following equations for v csmin , v csmax , and v compmax : cs min dson lpp csmin a ri v ?= _ 2 1 v75.0 cs max dson lpp loadmax csmax a ri i v + += _ ) 2 1 (v75.0 csmax ramp on in compmax v r t v v + ? = pf 100 )v2.0( where: v csmin is the minimum amplified voltage of the internal current sense amplifier at zero output current. v csmax is the maximum amplified voltage of the internal current sense amplifier at maximum output current. r dson_min is the low - side mosfet minimum on resistance. the zero - curr ent level voltage of the current sense amplifier is 0.75 v. i lpp is the peak - to - peak ripple current in the inductor. i loadmax is the maximum output dc load current. v compmax is the maximum voltage at the comp pin. 100 pf i s an internal para meter. t on is the high - side driver (dh) on time.
ADP1850 rev. 0 | page 18 of 32 input capacitor sele ction the input current to a buck converter is a pulse waveform. it is zero when the high - side switch is off and approximately equal to the load current when it is on. the input capacito r carries the input ripple current, allowing the input power source to supply only the direct current. the input capacitor needs sufficient ripple current rating to handle the input ripple, as well as an esr that is low enough to mitigate input voltage rip ple. for the usual current ranges for these converters, it is good practice to use two parallel ca pacitors placed close to the drains of the high - side switch mosfets (one bulk capacitor of sufficiently high current rating and a 10 f ceramic decoupling capacitor, typically). select an input bulk capacitor based on its ripple current rating. first, det ermine the duty cycle of the output. in out v v d = the input capacitor rms ripple current is given by )1( ddii o rms ?= where: i o is the output current. d is the duty cycle the minimum input capacitance required for a particular load is sw esr o pp o minin f dr iv ddi c ) ( )1( , ? ? = where: v pp is the desired input ripple voltage. r esr is the equivalent series resistance of the capacitor. if an mlcc capacitor is used, the esr is near 0, then the equation is simplified to sw pp o minin fv dd ic ? = )1( , the capacitance of ml cc is voltage dependent. the actual capacitance of the selected capacitor must be derated accord ing to the manufacturers specification . in addition, add more bulk capacitance, such as by using electrolytic or polymer capacitors, as neces sary for large ste p load transi ents. make sure the current ripple rating of the bulk capacitor exceeds the maximum input current ripple of a particular design. input filter normally a 0.1 f or greate r value bypass capacitor from the input pin (vin) to agnd is sufficient f or filtering out any unwanted switching noise. however, depending on the pcb layout, some switching noise can enter the adp 1850 internal circuitry ; therefore, it is recommended to have a low pass filter at the vin pin. connecting a resistor, between 2 ? an d 5 ?, in series with vin and a 1 f ceramic capacitor between vin and agnd creates a low pass filter that effectively filters out any unwanted glitches caused by the switching regulator. keep in mind that the input current could be larger than 100 ma when driving large mosfets. a 100 ma across a 5 ? resistor creates a 0.5 v drop, which is the same voltage drop in vcco. in this case, a lower resistor value is desirable. ADP1850 vin v in agnd 2 ?72? 1f 09440-033 figure 32 . input filter configuration boost capacitor sele cti on to lower system component count and cost, the adp 1850 has an integrated rectifier (equivalent to the boost diode) between vcco and bstx. choose a boost ceramic capacitor with a value b etween 0.1 f and 0.22 f; this capacitor provides the current for th e high - side driver during switching. inductor selection the ou tput lc filter smoothes the switched voltage at swx . for most applications, c hoose an inductor value such that the inductor ripple current is between 20% and 40% of the maximum dc output load current. generally, a larger inductor current ripple generates more power loss in the inductor and larger voltage ripples at the output. check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. choose the inductor value by the following equation: in out l sw out in v v if vv l ? ? = where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. ? i l is the peak - to - peak indu ctor ripple current.
ADP1850 rev. 0 | page 19 of 32 output capacitor sel ection choose the output bulk capacitor to set the desired output voltage ripple. the impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. th e impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (esr), and the equivalent series inductance (esl). the output voltage ripple can be approximated by ? ? ? ? ? ? ? ? + +??? esl sw out sw esr l out lf cf riv 4 8 1 wher e: ? v out is the output ripple voltage. ? i l is the inductor ripple current. r esr is the equivalent series resistance of the output capacitor (or the parallel combination of esr of all output capacitors). l esl is the equivalent series inductance of the outpu t capacitor (or the parallel combination of esl of all capacitors). solving c out in the previous equation yields esl sw l esr l out sw l out lfirivf i c ????? ? ? 4 1 8 usually th e capacitor impedance is dominated by esr. the maximum esr rating of the capacitor , such as in electrolytic or polymer capacitors, is provided in the manufacturers data sheet; therefore, output ripple reduces to esr l out riv ??? electrolytic capacitors also have significant esl, on the order of 5 nh to 20 nh, depending on type, size, and geometry. pcb trac es contribute some esr and esl, as well. however, using the maximum esr rating from the capacitor data sheet usually provides some margin such that measuring the esl is not usually required. in the case of output capacitors where the impedance of the esr and esl are small at the switching frequency, for instance, where the output cap a cit or is a bank of parallel mlcc capaci - tors, the capacitive impedance dominates and the output capacitance equation reduces to sw out l out fv i c ? ? ? 8 make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. during a load step transient on the output, for instance, when the load is suddenly increased, the output capacitor supplies the load until the control loop ha s a chance to ramp the inductor current. this initial output voltage deviation results in a voltage droop or undershoot . the ou tput capacitance, assuming 0 ? esr , required to satisfy the voltage droop requirement is approximated by sw droop step out fv i c ? ? ? where: ? i step is the step load. ? v droop is the voltage droop at the output. when a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. the output capacitance required to satisfy the output overshoot requirement can be approximated by 2 2 2 ) ( out overshoot out step out v vv li c ? ?+ ? ? where: ? v overshoot is the overshoot voltage during the step load. select the largest output capacitance given by any of the previous three equations. mosfet selection th e choice of mosfet directly affects the dc - to - dc converter performance. a mosfet with low on resistance reduces i 2 r losses, and low gate charge reduces transition losses. the mosfet should have low thermal resistance to ensure that the power dissipated in the mosfet does not result in excessive mosfet die temperature. the high - side mosfet carries the load current during on time and usually carries most of the transition losses of the converter. typically, the lower the on resistance of the mosfet, the highe r the gate charge and vice versa. therefore, it is important to choose a high - side mosfet that balances the two losses. the conduction loss of the high - side mosfet is determined by the equation ? ? ? ? ? ? ? ? ? in out dson load c v v rip 2 )( where: r dson is the mosfet on resistanc e. the gate charging loss is approximated by the equation sw g pv g fqvp ? w here : v pv is the gate driver supply voltage. q g is the mosfet total gate charge. note that the gate charging power loss is not dissipated in the mosfet but rather in the adp 1 850 internal drivers. this power loss should be taken into consideration when calculating the overall power efficiency.
ADP1850 rev. 0 | page 20 of 32 the high - side mosfet transition loss is approximated by the equation 2 )( sw fr load in t fttiv p + ? where: p t is the high - side mosfet switching loss power. t r is the rise time in charging the high - side mosfet. t f is the fall time in discharging the high - side mosfet. t r and t f can be estimated by rise driver gsw r i q t _ ? fall driver gsw f i q t _ ? where: q gsw is the gate charge of the mosfet during swit ching and is given in the mosfet data sheet. i driver_rise and i driver_fall are the driver current put out by the adp 1850 internal gate drivers. if q gsw is not given in the data sheet, it can be approximated by 2 gs gd gsw q qq +? where: q gd and q gs are the gate - to - drain an d gate - to - source charges given in the mosfet data sheet. i driver_rise and i dri ver _fall can be estimated by gate source on sp dd rise driver r r vv i + ? ? _ _ gate sink on sp fall driver r r v i + ? _ _ where: v dd is the input supply voltage to the driver and is between 2.75 v and 5 v, depending on the input voltage. v sp is the switching point where the mosfet fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the mosfet data sheet. r on_source is the on resistance of the adp 1850 internal driver, given in table 1 when charging the mosfet. r on_sink is the on resistance of the adp 1850 internal driver, given in table 1 when discharging the mosfet. r gate is the on gate resistance of mosfet given in the mosfet data sheet. if an external gate resistor is added, add this external resistance to r gate . the total power dissipation of the high - side mosfet is the sum of conduction and transition losses: t c hs ppp +? the synchronous rectifier, or low - side mosfet, carries the inductor current when the high - side mosfet is off. the low - side mosfet transition loss is small and can be neglected in the calculation. for high input voltage and low output voltage, the low - side mosfet carries the current mos t of the time. therefore, to achieve high efficiency, it is critical to optimize the low - side mosfet for low on resistance. in cases where the power loss exceeds the mosfet rating or lower resistance is required than is available in a single mosfet, conne ct multiple low - side mosfets in parallel. the equation for low - side mosfet conduction power loss is ? ? ? ? ? ? ?? in out dson load cls v v rip 1 )( 2 there is also additional power loss during the time, known as dead time, between the turn - off of the high - side switch and the turn -o n of the low - side switch, when the body diode of the low - side mosfet conducts the output current. the power loss in the body diode is given by o sw df bodydiode iftv p = where: v f is the forward voltage drop of the body diode, typically 0.7 v. t d is the dead t ime in the ADP1850, typically 30 ns when drivi ng some medium - size mosfets with input capacitanc e, c iss , of approximately 3 nf. the dead time is not fixed. its effective value varies with gate drive resistance and c iss , so p b odydiode increases in high load current designs and low voltage designs. then the power loss in the low - side mosfet is bodydiode cls ls ppp += note that mosfet, r dson , increases with increasing tempera - ture with a typical temperature coefficient of 0.4%/ o c. the mosfet junction temperatur e (t j ) rise over the ambient temperature is t j = t a + ja p d where: ja is the thermal resistance of the mosfet package. t a is the ambient temperature. p d is the total power dissipated in the mosfet.
ADP1850 rev. 0 | page 21 of 32 loop compensation (s ingle p hase o peration) as with most current mode step - down controller, a transcon - duc tance error amplifier is used to stabilize the external voltage loop. compensating the adp 1850 i s fairly easy; an rc compen - sator is needed between comp x and agnd. figure 33 shows the configuration of the compensation components: r comp , c comp , and c c2 . because c c2 is very small compared to c comp , to simplify calculation, c c2 is ignored for the stability compensation analysis. ADP1850 fbx c comp g m 0.6v compx agnd r comp c c2 09440-034 figure 33 . compensation components the open loop gain transfer function at angular frequency, s, is given by )()( )( szsz v v ggsh filter comp out ref cs m = (1) where: g m is the transconductance of the error amplifier , 500 s . g cs is the tranconductanc e of the power stage . z comp is the impedance of the compensation network. z f ilter is the im pedance of the output filter. v ref = 0.6 v . g cs with units of a/v is given by min dson cs cs ra g _ 1 = (2) where: a cs is the current sense gain of either 3 v/v, 6 v/v, 12 v/v, or 24 v/v set by the gain resistor between dl x and pgnd x. r dson_min is the low -si de mosfet minimum on resistance. if a sense resistor, r s , is added in series with the low - side fet, then g cs becomes ) ( 1 _ s min dson cs cs r ra g + = because the zero produced by the esr of the output capacitor is not needed to stabilize the control loop, assuming esr is small the esr is ignored for analysis. then z filter is given by out filter sc z 1 = (3) bec ause c c2 is small relative to c comp , z comp can be simplified to comp comp comp comp comp comp sc c sr sc rz + =+= 1 1 (4) at th e crossover frequency, the open -lo op transfer function is un ity or 0 db, h (f cross ) = 1. combining equation 1 and equation 3, z comp at the crossover frequency can be written as ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ref out out cs m cross cross comp v vc gg f fz 2 )( (5) the zero produced by r comp and c comp is comp comp zero cr f = 2 1 (6) at the crossover frequency, equation 4 can be shown as cross zero cross comp cross comp f ff rfz 2 )( 2 + = (7) combining equations 5 and equation 7 and solving for r comp gives ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ref out out cs m cross zero cross cross comp v vc gg f ff f r 2 2 2 (8) choose the crossover and zero frequencies as follows: 12 sw cross f f = (9) 484 sw cross zero ff f == (10) substituting equ ation 2, equation 9, and equation 10 into equation 8 yields ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ref out out m cross dson cs comp v vc g f ra r 2 97.0 (11) where: g m is the transconductan ce of the error amplifier , 500 s . a cs is the current sense gain of 3 v/v, 6 v/v, 12 v/v , or 24 v/v. r dson is on resistance of the low -si de mosfet. v ref = 0.6 v . and combining equation 6 and equation 10 yields cross comp comp fr c = 2 (12) note that the previous simplified compensation equations for r comp and c comp yield reasonable results in f cross and phase margin assuming that the compens ation ramp current is ideal. varying the ramp current or deviating the ramp current from ideal can affect f cross and phase margin. and lastly , set c c2 to comp c comp c cc ?? 10 1 20 1 2 (13)
ADP1850 rev. 0 | page 22 of 32 configuration and loop compensation ( dual -p hase o peration) in dual - phase o peration, the two outputs of the switching regulators are shorted together and can source more than 50 a of output current depending on the selection of the power components. internal parameters in the ADP1850 are optimized and trimmed in the factory to minimize the mismatch in output currents betwee n the two channels. see figure 34 and figure 47 for a configuration of a typical dual - phase application circuit. note that fb1 shorts to fb2 , ss1 to ss2, and comp1 to comp2, wh ere the outputs of the two error amplifiers are shared. furthermore, the controller needs to be placed in forced pwm operation by connecting sync to vcco or logic high. the equations for calculating the loop compensatio n compo - nents are identical to the single - phase operation, but the combined value of g m of the error amplifiers, the modulator gain and the effective f sw are all doubled. ramp1 r ramp1 vin dh1 bst1 sw1 ilim1 fb1 dl1 pgnd1 ramp2 dh2 bst2 sw2 ilim2 fb2 dl2 pgnd2 en1 en2 vdl vcco trk1 trk2 sync freq comp1 comp2 ss1 ss2 agnd r csg1 r1 r2 m1 m2 r csg2 m3 l2 l1 v outx v in v in m4 r ramp2 pgood1 pgood2 ADP1850 hi lo 09440-002 figure 34 . dual - phase circuit switching noise and oversho ot reduction in any high speed step - down regulator, high frequency noise (generally in the range of 50 mhz to 100 mhz) and voltage overshoot are always present at the gate, the switch node (sw), and the drains of the external mosfets. the high frequency no ise and overshoot are caused by the parasitic capacitance, c gd , of the external mosfet and the parasitic inductance of the gate trace and the packages of the mosfets. when the high current is switched, electromagnetic interference (emi) is generated, which can affect the operation of the surrounding circuits. to reduce voltage ri nging and noise, it is recommended to add an rc snubber bet ween sw x and pgnd x for high current applications , as illustrated in figure 35 . in most applications, r snub is typically 2 ? to 4 ?, and c snub typically 1.2 nf to 3 nf. r snub can be estimated by oss mosfet snub c l r 2 ? and c snub can be estimated by oss snub cc ? where : l mosfet is the total parasitic inductance of the high -s ide and low - side mosfets, typically 3 nh, and is package dependent. c oss is the total output capacitance of the high - side and low - side mosfets given in the mosfet data sheet. the size of the rc snubber components need s to be chosen correctly to handle the power dissipation. the power dissipated in r snub is sw snub in snub fcvp = 2 in most applications, a component s ize 0805 for r snub is sufficient . however, the use of an rc snubber reduces the overall efficiency , generally by an amount in the range of 0.1 % t o 0.5%. the rc snubber does not reduce the voltage overshoot. a resistor, shown as r rise in figure 35 , at the bstx pin helps to reduce overshoot and is generally between 2 ? and 4 ?. adding a resistor in series, typically between 2 ? and 4 ?, with the gate driver also helps to reduce overshoot. if a gate resistor is added, then r rise is not needed. v in ADP1850 (channel 1) dh1 vdl dl1 ilim1 r ilim1 sw1 bst1 pgnd1 r rise m1 m2 l v outx c snub c out r snub 09440-035 figure 35 . application circuit with a snubber
ADP1850 rev. 0 | page 23 of 32 voltage tracking the adp 1850 includes a tra cking feature that tracks a master voltage. this feature is especially important when the adp 1850 is providing separate power supply voltages to a single integrated circuit, such as the core and i/o voltages of a dsp , fpga, or microcon troller. in these ca ses, improper sequencing can cause damage to the load ic . in all tracking configurations, the output can be set as low as 0.6 v for a given operating condition. the soft start time setting of the master voltage should be longer than the soft start of the s lave voltage. this forces the rise time of the master voltage to be i mposed on the slave voltage . if the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relationship is not seen at the output. two tracki ng configurations are possible with the adp 1850: coincident and ratiometric trackings. coincident tracking the most common application is coincident tracking, used in core vs. i/o voltage sequencing and similar applica tions. coincident tracking force s the slave output voltage s ramp rate to be the same as the masters until the slave output reaches its regulation. connect the slave trk x input to a resistor divider from the master voltage that is the same as the divider used on the slave fb x pin. this force s the slave voltage to be the same as the master voltage. for coincident tracking, use r trkt = r top and r trkb = r bot , as shown in figure 37 . time sla ve vo lt age master vo lt age voltage (v) 09440-036 figure 36 . coincident tracking ADP1850 en2 en1 en fb2 fb1 trk1 ss1 vcco trk2 ss2 10k? 45.3k ? r trkb 10k? r trkt 20k? 1.1v 3.3v v out1_master c ss2 20nf c ss1 100nf r bot 10k? r top 20k? 1.8v v out2_slave 09440-037 figure 37 . example of a coincident tracking circuit the ratio of the slave output voltage to the master voltage is a function of the two dividers. trkb trkt bot top master out slave out r r r r v v 1 1 _ _ as the master voltage rises, the slave voltage rises identically. event ually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the trkx input continues to increase and thus removes itself from influencing the output voltage. to ensure that the output voltage accur acy is not compromised by the trkx pin being too close in voltage to the reference vol tage (v fb , typically 0.6 v) , make sure that the final value of the trkx voltage of the slave channel is at least 30 mv above v fb . ratiometric tracking ratiometric tracki ng limits the output voltage to a fraction of the master voltage , as illustrated in figure 38 and figure 39. the final trk x voltage of the slave channel should be set to at least 30 mv below the fb voltag e of the master channel. when the trk x voltage of the slave channel drops to a level thats below the minimum on - time condition, the slave channel operate s in pulse skip mode while keeping the output regulated and tracked to the master channel. also, when trk x or fb x drops below the pgood undervoltage threshold, the pgood signal gets tripped and becomes active low. time sla ve vo lt age master vo lt age voltage (v) 09440-038 figure 38 . ratiometric tracking ADP1850 en2 en1 en fb2 fb1 trk1 ss1 vcco trk2 ss2 10k? 45.3k ? r trkb 10k? r trkt 49.9k ? 0.6v 0.55v 3.3v v out1_master c ss2 20nf c ss1 37nf r bot 10k? r top 22.6k ? 1.8v v out2_slave 0.55v 09440-039 figure 39 . example of a ratiometric tracking circuit anoth er ratiometric tracking configuration is having the slave channel rise more quickly than the master channel, as shown in figure 40 and figure 41. the tracking circuits in figure 39 and figure 41 are virtually identical with t he exception that r trkb > r trkt as shown in figure 41.
ADP1850 rev. 0 | page 24 of 32 time sla ve vo lt age master vo lt age voltage (v) 09440-040 figure 40 . ratiometric tracking (slave channel has a faster ramp rate) ADP1850 en2 en1 en fb2 fb1 trk1 ss1 vcco trk2 ss2 10k? 45.3k ? r trkb 10k? r trkt 5k? 2.2v 3.3v v out1_master c ss2 20nf c ss1 100nf r bot 10k? r top 20k? 1.8v v out2_slave 09440-041 figure 41 . example of a ratiometric track ing circuit (slave channel has a faster ramp rate) i ndepdendent p ower stage i nput v oltage in addition to the single pow er supply configuration, the power stage input voltage of the dc - to - dc converter can come from a different voltage supply, as illustrated in figure 42. the range of the power stage input voltage ( v pin ) is 1 v to 20 v. for instance , the bias input voltage ( v in ) is 5 v, v pin can be as low as 1 v or as high as 20 v. the user needs to make sure that the minimum or the maximum duty cycle is not violated in this operatin g condition. furthermore, note that r ramp is connected to v pin . v in = 2.7v to 20v vin ADP1850 dh1 fb1 dl1 pgnd1 sw1 v out1 v pin = 1v to 20v ramp1 r ramp1 dh2 ramp2 fb2 dl2 pgnd2 sw2 v out2 v pin = 1v to 20v r ramp2 09440-042 figure 42 . independent power stage input voltage (simplified schematic )
ADP1850 rev. 0 | page 25 of 32 pcb layout guideline s in any switching converter, there are some circuit paths that carry high di/dt, which can create spikes and noise. some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant ir voltage drops. the key to proper pcb layout of a switching converter is to identify these critical paths and arrange the components and the copper area accord ingly. when designing pcb layouts, be sure to keep high current loops small. in addition, keep compensation and feedback components away from the switch nodes and their associated components. the following is a list of recommended layout practices for the synchronous buck controller, arranged by decreasing order of importance. mosfets, input bulk capacitor, and bypas s capacitor the current waveform in the top and bottom fets is a pulse with very high di/dt; therefore, the path to, through, and from each in dividual fet should be as short as possible, and the two paths should be commoned as much as possible . in designs that use a pair of d - pak , or a pair of so - 8 f e ts , on one side of the pcb, it is best to counter - rotate the two so that the switch node is on o ne side of the pair. this allows the high - side fet s drain to be bypassed to the low - side fet s source with a sui table ceramic bypass capacitor placed as close as possible to the fets. close proximity of the bypass capacitor mini mizes the inductance around the loop through the fets and capacitor. the recommended bypass ceramic c apacitor values range from 1 f to 22 f, dependin g on the output current. the ceramic bypass capacitor is usually connected to a larger value bulk filter capacitor and should be gro unded to the pgndx plane. high current and current sense paths part of the adp 1850 architecture is sensing the current across the low - side fet between the swx and pgndx pins. the switching gnd currents of one channel creates noise and can be picked up by the other channel. it is essential to have kelvin sensing connection between swx and the drain of the respective low - side mosfet, and between pgndx and the source of the respective low - side mosfet, as illustrated in figure 43. pl ace these kelvin connections very close to the fets to achieve accurate current sensing. figure 43 illustrates the proper connection technique for the sw1/sw2, pgnd1/ pgnd2, and pgnd plane. ADP1850 dh1 sw1 m2 l1 v out1 v in m1 pgnd plane cout1 cin1 c decouple1 m3 l2 v out2 v in m4 cout2 cin2 c decouple2 23 24 21 22 19 20 17 18 pgnd2 dl2 sw2 dh2 dl1 pgnd1 agnd plane kelvin connections 09440-043 figure 43 . grounding technique for two channels signal paths the negative terminals of vin bypass, compensation components, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to a small agnd plane. t hese connections shoul d attach from their re spective pins to the agnd plane and should be as short as possible. no high current or high di/dt signals should be connected to this agnd plane. the agnd area should be connected through one wide trace to the negative terminal of the output filter capacitors. pgnd plane the pgndx pin handles a high di/dt gate drive current returning from the source of the low side mosfet. the voltage at this pin also establishes the 0 v reference for the overcurrent limit protection function and the ilimx pin. a pgnd plane should connect the pgndx pin and the vdl bypass capacitor, 1 f, through a wide and direct path to the source of the low side mosfet. the placement of cin is critical for controlling ground bounce. the negative terminal of cin must be placed very close to the source of the low - side mosfet. feedback and current limit sense paths avoid long traces or large copper areas at the fbx and ilimx pins, which are low - level signal inputs that are sensitive to capacitive and inductive noise pic kup. it is best to position any series resistors and capacitors as close as possible to these pins. avoid running these traces close and/or parallel to high di/dt traces.
ADP1850 rev. 0 | page 26 of 32 switch node the switch node is the noisiest place in the switcher circuit with larg e ac and dc voltages and currents. this node should be wide to minimize resistive voltage drop. to minimize capacitively coupled noise, the total area should be small. place the fets and inductor close together on a small copper plane to minimize series resistance and keep the copper area small. gate driver paths gate drive traces (dh and dl) handle high di/dt and tend to produce noise and ringing. they should be as short and direct as possible. if vias are needed, it is best to use two relatively large one s in parallel to reduce the peak current density and the current in each via. if the overall pcb layout is less than optimal, slowing down the gate drive slightly can be helpful to reduce noise and ringing. it is occasionally helpful to place small value resistors, such as between 2 and 4 , on the dh x and dl x pins . these can be populated with 0 resistors if resistance is not needed. note that the added gate resistance increases the switching rise and fall times , as well as increasing switching power lo ss in the mosfet. output capacitors the negative terminal of the output filter capacitors should be tied close to the source of the low side fet. doing this helps to minimize voltage differences between agnd and pgndx.
ADP1850 rev. 0 | page 27 of 32 typical o perating circuits vcco vcco 187k ? en1 sync 100nf to vin 187k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 ADP1850 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 42.2k ? 47pf 330pf 23.2k ? 47pf 560pf 100nf 22pf 1f 0.1 f 0.1 f 1f 1f 2.1k ? l2 m4 m3 22k ? cout 22 cout 21 cin 2 v out2 1.8v 14a v in 2.1k ? l1 m2 m1 22k ? cout 12 cout 11 cin 1 v out1 3.3v 14a v in = 10v to 18v 20k? 10k? cin 1 , cin 2 : 10f/x7r/25v/1210 2, grm32dr71e106ka12, murata cout 11 , cout 21 : 330f/6.3v/poscap 2, 6tpf330m9l, sanyo cout 12 , cout 22 : 22f/x5r/0805/6.3v 3, grm21br60j226me39, murata f sw = 600khz cin: 150f/20v, os-con, 20sep150m, sanyo l1, l2: 1.2 h, wurth elektronik, 744325120 m1, m3: bsc080n03ls m2, m4: bsc030n03ls 45.3k ? 10k ? 2? 2 ? cin 22pf 09440-044 figure 44 . typical 14 a operating circuit
ADP1850 rev. 0 | page 28 of 32 vcco vcco 150k ? en1 sync 100nf to vin 150k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 ADP1850 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 28k ? 33pf 560pf 10k ? 100pf 1.5nf 100nf 1f 0.1 f 0.1 f 1f 1f 2.8k ? l2 m2b m 2a 22k ? cout 2 cin 2 v out2 1.8v 5a v in 2.8k ? l1 m1b m1a 22k ? cout 1 cin 1 v out1 5v 5a v in = 10v to 20v 20k? 10k? cin 1 , cin 2 : 10f/x5r/16v/1206 2, grm31cr61c106ka88, murata m1, m2: si944dy or bson03md cout 1 , cout 2 : 22f/xr5/1210/6.3v 3, grm32dr60j226ka01, murata f sw = 750khz, pulse skip mode l1: 2 h, wurth elektronik, 744310200 l2: 1.15 h, wurth elektronik, 744310115 73.2k ? 10k ? 2? 2 ? 84.5k ? 09440-045 figure 45 . typical low current operating circuit
ADP1850 rev. 0 | page 29 of 32 vcco vcco 20k ? en1 sync 100nf to vin 20k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 ADP1850 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 5.34k ? 33pf 1.8nf 8.66k ? 33pf 1nf 100nf 1f 0.1 f 0.1 f 1f 1f 4.99k ? l2 m4 m3 47k ? cout 2 cin 2 v out2 1.8v 1.8a v in 4.99k ? l1 m2 m1 47k ? cout 1 cin 1 v out1 1.05v 1.8a v in = 3v to 5.5v 20k? 10k? cin 1 , cin 2 : 4.7f/x5r/16v/0805 2, grm219r60j475ke19, murata cout 1 , cout 2 : 22f/xr5/0805/6.3v, grm21br60j226me39, murata f sw = 800khz, pulse skip mode l1, l2: 1 h, toko d62lcb1r0m m1, m2, m3, m4: si2302ads, sot23 7.5k ? 10k ? 5? 78.7k ? 09440-046 figure 46 . typical low current application with v in < 5.5 v
ADP1850 rev. 0 | page 30 of 32 l2 vin cin 22 cin 21 m5 m6 m7 m8 1.74k ? 22k? cout 21 cout 22 to vcco 137k ? en1 sync to vin 137k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 c o mp1 ramp1 ss1 pgood1 ilim1 bst1 ADP1850 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 8.87k ? 180pf 3.3nf 100nf 22pf 1f 0.1 f 0.1 f 1f 1f to vcco to fb1 to ss1 to comp1 v out1 1.09v 50a cin 11 , cin 12 , cin 21 , cin 22 : 10f/x7r/25v/1210, murata cout 11 , cout 21 , 2sepc560mz 3, 560f, oscon, sanyo cout 12 , cout 22 : grm31cr60j476me19 2, 47v/1206/6.3v, murata f sw = 300khz cin = 180f/16v 4, 16sep180m, os-con, sanyo m1, m2, m5, m6: bsc080n03is m3, m4, m7, m8: bsc030n03ls l1, l2: ser1408-301, 300nh, coilcraft; or 744355147, 0.4h, wurth electronik 8.3k ? 10k ? 2? 2 ? l1 v in = 10v to 14v cin 12 cin 11 m1 m2 cin m3 m4 1.74k ? 22k? cout 11 cout 12 22pf 09440-047 figure 47 . dual - phase circuit , 50 a output
ADP1850 rev. 0 | page 31 of 32 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.65 3.50 sq 3.45 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 48 . 32 - lead lead frame chip scale package [lfcsp _wq ] 5 mm 5 m m body, very very thin quad (cp - 32 - 11 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADP1850a cpz -r7 ?40c to + 8 5c 32- lead lead fr ame chip scale package [lfcsp _wq ] cp -32-11 ADP1850sp - evalz evaluation board in single - phase mode with 14 a output ADP1850dp - evalz evaluation board in dual - phase mode with 50 a output 1 z = rohs compliant part.
ADP1850 rev. 0 | page 32 of 32 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09440-0-11/10(0)

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